|Study of an In-order SMT Architecture and Grouping Schemes
Byung In Moon, Moon Gyung Kim, In Pyo Hong, Ki Chang Kim, and Yong Surk Lee
International Journal of Control, Automation, and Systems, vol. 1, no. 3, pp.339-350, 2003
Abstract : In this paper, we propose a simultaneous multithreading (SMT) architecture that improves
instruction throughput by exploiting instruction level parallelism (ILP) and thread level
parallelism (TLP). The proposed architecture issues and completes instructions belonging to the
same thread in exact program order. The issue and completion policy greatly reduces the design
complexity and hardware cost of our architecture, compared with others that employ out-oforder
issue and completion. On the other hand, when the instructions belong to different threads,
the issue and completion orders for those instructions may not necessarily be identical to the
fetch order. The processor issues instructions simultaneously from multiple threads to functional
units by exploiting ILP and TLP, and by dynamic resource sharing. That parallel execution notably
improves performance and resource utilization with minimal additional hardware cost over
the conventional superscalar processors.
This paper proposes an SMT architecture with grouping as well as one without grouping.
Without grouping, all threads dynamically and flexibly share most resources. On the other hand,
in the SMT architecture with grouping, in which resources and threads are divided into several
groups for design simplification, resources are shared only among threads belonging to the same
group as those resources. Simulation results show that our processors with four and eight threads
improve performance by three or more times over the conventional superscalar processor with
comparable execution resources and policies, and that reasonable grouping reduces the design
complexity of SMT processors with little negative effect on performance.
Keyword : Multithreading, SMT, ILP, TLP, in-order issue and completion, grouping.